The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology which is effective for application to a static RAM (i.e., Random Access Memory) of the so-called "ECL interface bipolar-CMOS (i.e., Complementary MOS) construction" having an interchangeability with an ECL (i.e., Emitter Coupled Logic) circuit.
There is known a static RAM having the bipolar CMOS construction, in which memory cells are constructed of the CMOS circuit and which is structured so as to raise the degree of integration, reduce the power consumption and to use an ECL circuit in an input/output circuit. The static RAM of the bipolar CMOS construction is exemplified and discussed on pp. 38 to 39 and 284 of ISSCC DIGEST OF TECHNICAL PAPERS, 1989. Moreover, counter-measure schemes for overcoming the switching noise in the ECL circuit are dlsclosed in JP-A-60-90428 and JP-A-56-36231.